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CY7C145 CY7C144
8K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
Features
* True Dual-Ported memory cells which allow simultaneous reads of the same memory location * 8K x 8 organization (CY7C144) * 8K x 9 organization (CY7C145) * 0.65-micron CMOS for optimum speed/power * High-speed access: 15ns * Low operating power: ICC = 160 mA (max.) * Fully asynchronous operation * Automatic power-down * TTL compatible * Master/Slave select pin allows bus width expansion to 16/18 bits or more * Busy arbitration scheme provided * Semaphores included to permit software handshaking between ports * INT flag for port-to-port communication * Available in 68-pin PLCC, 64-pin and 80-pin TQFP * Pin compatible and functionally equivalent to IDT7005/IDT7015 are included on the CY7C144/5 to handle situations when multiple processors access the same piece of data. Two ports are provided permitting independent, asynchronous access for reads and writes to any location in memory. The CY7C144/5 can be utilized as a standalone 64/72-Kbit dual-port static RAM or multiple devices can be combined in order to function as a 16/18-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 16/18-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory. Each port has independent control pins: chip enable (CE), read or write enable (R/W), and output enable (OE). Two flags, BUSY and INT, are provided on each port. BUSY signals that the port is trying to access the same location currently being accessed by the other port. The interrupt flag (INT) permits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power-down feature is controlled independently on each port by a chip enable (CE) pin or SEM pin.
Functional Description
The CY7C144 and CY7C145 are high-speed CMOS 8K x 8 and 8K x 9 dual-port static RAMs. Various arbitration schemes
Logic Block Diagram
R/W L CE L OE L R/W R CE R OE R
(7C145) I/O 8L I/O7L I/O0L BUSYL
[1, 2]
I/O CONTROL
I/O CONTROL
I/O 8R (7C145) I/O 7R I/O 0R BUSYR A 12R
[1, 2]
A 12L A 0L ADDRESS DECODER MEMORY ARRAY ADDRESS DECODER
A 0R
CEL OEL R/W L SEM L INT L [2]
INTERRUPT SEMAPHORE ARBITRATION
CE R OE R R/W R SEM R INT R [2]
M/S
C144-1
Notes: 1. BUSY is an output in master mode and an input in slave mode. 2. Interrupt: push-pull output and requires no pull-up resistor.
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134
*
408-943-2600 November 1996
CY7C145 CY7C144
Pin Configurations
68-Pin PLCC Top View
NC OE L R/W L SEM L CEL I/O 1L I/O 0L
[4]
NC NC VCC A12L A 11L A 10L A9L
A8L A7L
9876 I/O2L I/O3L I/O4L I/O5L GND I/O6L I/O7L VCC GND I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R I/O6R 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 I/O7R
[3]
5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 CY7C144/5 52 51 50 49 48 47 46 45 44
A6L A5L A4L A3L A2L A1L A0L INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R C144-2
2728 29 30 3132 33 34 35 36 37 38 39 40 41 42 43 R/W R SEM R CER NC NC GND A12R A 11R A10R A 9R A8R NC OER A7R A6R A7L 51 50 A5R 49
64-Pin TQFP Top View
SEML R/WL I/O1L I/O0L A12L A11L A10L OEL CEL NC VCC A9L A8L 52 A6L A5L
64
63
62 61
60
59
58
57
56 55
54
I/O2L I/O3L I/O4L I/O5L GND I/O6L I/O7L VCC GND I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R
53
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
48 47 46 45 44 43 42
A4L A3L A2L A1L A0L INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R
CY7C144
41 40 39 38 37 36 35 34
17
18
19 20
21
22
23
24
25 26
27
28
29
30 31
32
16
33
I/O6R
R/WR
SEMR
GND
CER NC
A9R
A8R
A7R
I/O7R
OER
A12R
Notes: 3. I/O8R on the CY7C145. 4. I/O8L on the CY7C145.
2
A11R A10R
A6R A5R
C144-3
CY7C145 CY7C144
Pin Configurations (continued)
80-Pin TQFP Top View
I/O1L I/O0L SEM L R/W L I/O8L OE L A12L A11L CE L NC A10L VCC
A9L
A8L
A7L 64
NC NC
A6L
80
79
78 77
76
75
74
73
72 71
70
69
68
67
66 65
63 62
NC I/O 2L I/O 3L I/O 4L I/O 5L GND I/O 6L I/O 7L V CC NC GND I/O0R I/O1R I/O2R V CC I/O 3R I/O 4R I/O 5R I/O 6R NC
1 2 3 4 5 6 7 8
61
NC NC
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42
NC A5L A4L A3L A2L A1L A0L INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R NC NC
9 10 11 12 13 14 15 16 17 18 19 21 22 23 24 25 26 27 28
CY7C145
29 30
31
32
33
34
35 36
37
38 39 NC
I/O7R
R/WR
SEMR
CER
GND
NC
NC NC
NC
40
20
41
OER
A9R
A8R
A7R
A6R
A12R
Pin Definitions
Left Port I/O0L-7L(8L) A0L-12L CEL OEL R/WL SEML Right Port I/O0R-7R(8R) A0R-12R CER OER R/WR SEMR Data bus Input/Output Address Lines Chip Enable Output Enable Read/Write Enable Semaphore Enable. When asserted LOW, allows access to eight semaphores. The three least significant bits of the address lines will determine which semaphore to write or read. The I/O0 pin is used when writing to a semaphore. Semaphores are requested by writing a 0 into the respective location. Interrupt Flag. INTL is set when right port writes location 1FFE and is cleared when left port reads location 1FFE. INTR is set when left port writes location 1FFF and is cleared when right port reads location 1FFF. Busy Flag Master or Slave Select Power Ground Description
INTL
INTR
BUSYL M/S VCC GND
BUSYR
I/O8R
3
A11R A10R
A5R
C144-4
CY7C145 CY7C144
Selection Guide
7C144-15 7C145-15 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum Standby Current for ISB1 (mA) 15 220 60 7C144-25 7C145-25 25 180 40 7C144-35 7C145-35 35 160 30 7C144-55 7C145-55 55 160 30
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ..................................... -65C to +150C Ambient Temperature with Power Applied .................................................. -55C to +125C Supply Voltage to Ground Potential..................-0.5V to +7.0V DC Voltage Applied to Outputs in High Z State .....................................................-0.5V to +7.0V DC Input Voltage ..............................................-0.5V to +7.0V
[5]
Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current.................................................... >200 mA
Operating Range
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 5V 10% 5V 10%
Electrical Characteristics Over the Operating Range
7C144-15 7C145-15 Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 ISB2 ISB3 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current Operating Current Standby Current (Both Ports TTL Levels) Standby Current (One Port TTL Level) GND < VI < VCC Outputs Disabled, GND < VO < VCC VCC = Max., IOUT = 0 mA Com'l Outputs Disabled Ind CEL and CER > VIH, f = fMAX[7] CEL or CER > VIH, f = fMAX[7] Com'l Ind Com'l Ind Com'l Ind Com'l Ind 125 15 130 -10 -10 Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 4.0 mA Min. 2.4 0.4 2.2 0.8 +10 +10 220 60 -10 -10 2.2 0.8 +10 +10 180 190 40 50 110 120 15 30 100 115 mA mA mA mA Max. 7C144-25 7C145-25 Min. 2.4 0.4 Max. Unit V V V V A A mA
Standby Current Both Ports (Both Ports CMOS Levels) CE and CER > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, f = 0[7] Standby Current (One Port CMOS Level) One Port CEL or CER > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, Active Port Outputs, f = fMAX[7]
ISB4
Notes: 5. Pulse width < 20 ns. 6. TA is the "instant on" case temperature. 7. fMAX = 1/t RC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby I SB3.
4
CY7C145 CY7C144
Electrical Characteristics Over the Operating Range (continued)
7C144-35 7C145-35 Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 ISB2 ISB3 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current Operating Current Standby Current (Both Ports TTL Levels) Standby Current (One Port TTL Level) GND < VI < VCC Outputs Disabled, GND < VO < VCC VCC = Max., IOUT = 0 mA Outputs Disabled CEL and CER > V IH, f = fMAX[7] CEL or CER > VIH, f = fMAX[7] Com'l Ind Com'l Ind Com'l Ind Com'l Ind Com'l Ind -10 -10 Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 4.0 mA 2.2 0.8 +10 +10 160 180 30 40 100 110 15 30 90 100 -10 -10 Min. 2.4 0.4 2.2 0.8 +10 +10 160 180 30 40 100 110 15 30 90 100 mA mA mA mA Max. 7C144-55 7C145-55 Min. 2.4 0.4 Max. Unit V V V V A A mA
Standby Current Both Ports (Both Ports CMOS Levels) CE and CER > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, f = 0[7] Standby Current (One Port CMOS Level) One Port CEL or CER > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, Active Port Outputs, f = fMAX[7]
ISB4
Capacitance[8]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 10 15 Unit pF pF
Note: 8. Tested initially and after any design or process changes that may affect these parameters.
5
CY7C145 CY7C144
AC Test Loads and Waveforms
5V R1=893 OUTPUT C = 30 pF R2=347 OUTPUT C=30pF VTH =1.4V (a) Normal Load (Load1)
C144-5
5V R1=893 OUTPUT C = 5 pF R2=347
RTH =250
(b) Thevenin Equivalent (Load 1)
C144-6
(c) Three-State Delay (Load 3)
C144-7
ALL INPUT PULSES OUTPUT C = 30 pF 3.0V GND 10% 90% 90% 10% 3 ns
C144-9
3 ns Load (Load 2)
C144-8
Switching Characteristics Over the Operating Range[9]
7C144-15 7C145-15 Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tLZCE
[10, 11,12] [10, 11,12]
7C144-25 7C145-25 Min. 25 Max.
7C144-35 7C145-35 Min. 35 Max.
7C144-55 7C145-55 Min. 55 Max. Unit ns 55 3 ns ns 55 25 3 25 3 25 0 55 ns ns ns ns ns ns ns ns
Description Read Cycle Time Address to Data Valid Output Hold From Address Change CE LOW to Data Valid OE LOW to Data Valid OE Low to Low Z OE HIGH to High Z CE LOW to Low Z CE LOW to Power-Up CE HIGH to Power-Down
Min. 15
Max.
15 3 15 10 3 10 3 10 0 15 0 3 3 3
25 3 25 15 3 15 3 15 0 25
35
35 20 20 20 35
tHZOE
[10, 11,12]
tHZCE[10, 11,12] CE HIGH to High Z tPU[12] tPD
[12]
Notes: 9. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOI/IOH and 30-pF load capacitance. 10. At any given temperature and voltage condition for any given device, tHZCE is less than t LZCE and t HZOE is less than t LZOE. 11. Test conditions used are Load 3. 12. This parameter is guaranteed but not tested.
6
CY7C145 CY7C144
Switching Characteristics Over the Operating Range[9] (continued)
7C144-15 7C145-15 Parameter WRITE CYCLE tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE tWDD
[11,12] [11,12]
7C144-25 7C145-25 Min. 25 20 20 2 0 20 15 0 Max.
7C144-35 7C145-35 Min. 35 30 30 2 0 25 15 0 Max.
7C144-55 7C145-55 Min. 55 45 45 2 0 40 25 0 Max. Unit ns ns ns ns ns ns ns ns 25 3 70 40 ns ns ns ns
Description Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold From Write End Address Set-Up to Write Start Write Pulse Width Data Set-Up to Write End Data Hold From Write End R/W LOW to High Z R/W HIGH to Low Z Write Pulse to Data Delay Write Data Valid to Read Data Valid BUSY LOW from Address Match BUSY HIGH from Address Mismatch BUSY LOW from CE LOW BUSY HIGH from CE HIGH Port Set-Up for Priority R/W LOW after BUSY LOW R/W HIGH after BUSY HIGH BUSY HIGH to Data Valid INT Set Time INT Reset Time SEM Flag Update Pulse (OE or SEM) SEM Flag Write to Read Time SEM Flag Contention Window
Min. 15 12 12 2 0 12 10 0
Max.
10 3 30 25 3
15 3 50 30
20 60 35
[13]
tDDD[13]
BUSY TIMING[14] tBLA tBHA tBLC tBHC tPS tWB tWH tBDD tINS tINR tSOP tSWRD tSPS 15 15 15 15 5 0 13 15 15 15 10 5 5 10 5 5 5 0 20 25 25 25 15 5 5 20 20 20 20 5 0 30 35 25 25 20 5 5 20 20 20 20 5 0 30 55 35 35 30 30 30 30 ns ns ns ns ns ns ns ns ns ns ns ns ns
INTERRUPT TIMING[14]
SEMAPHORE TIMING
Notes: 13. For information on part-to-part delay through RAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay waveform. 14. Test conditions used are Load 2.
7
CY7C145 CY7C144
Switching Waveforms
Read Cycle No. 1 (Either Port Address Access)[15, 16]
tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
C144-10
Read Cycle No. 2 (Either Port CE/OE Access)[15, 17, 18]
SEM or CE OE tACE tDOE tHZOE tHZCE
tLZOE tLZCE DATA OUT tPU ICC ISB
DATA VALID tPD
C144-11
Read Timing with Port-to-Port Delay
(M/S=L)[19, 20]
tWC
ADDRESSR R/WR
MATCH
t PWE
t
SD
t
HD
DATAIN R
VALID
ADDRESSL
MATCH tDDD
DATA OUTL tWDD
VALID
C144-12
Notes: 15. R/W is HIGH for read cycle. 16. Device is continuously selected CE = LOW and OE = LOW. This waveform cannot be used for semaphore reads. 17. Address valid prior to or coincident with CE transition LOW. 18. CEL = L, SEM = H when accessing RAM. CE = H, SEM = L when accessing semaphores. 19. BUSY = HIGH for the writing port. 20. CEL = CE R = LOW.
8
CY7C145 CY7C144
Switching Waveforms (continued)
Write Cycle No. 1: OE Three-State Data I/Os (Either Port) [21, 22, 23]
tWC ADDRESS tSCE SEM OR CE tAW R/W tSA DATA IN tPWE tSD DATA VALID tHD tHA
OE t HIGH IMPEDANCE
C144-13
tHZOE DATA OUT
LZOE
Write Cycle No. 2: R/W Three-State Data I/Os (Either
Port)[21, 23, 24]
tWC
ADDRESS tSCE SEM OR CE tSA R/W tAW tPWE tHA
tSD DATA IN tHZWE DATA OUT DATAVALID
tHD
tLZWE HIGH IMPEDANCE
C144-14
Notes: 21. The internal write time of the memory is defined by the overlap of CE or SEM LOW and R/W LOW. Both signals must be LOW to initiate a write, and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 22. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + t SD) to allow the I/O drivers to turn off and data to be placed on the bus for the required tSD. If OE is HIGH during a R/W controlled write cycle (as in this example), this requirement does not apply and the write pulse can be as short as the specified t PWE. 23. R/W must be HIGH during all address transitions. 24. Data I/O pins enter high impedance when OE is held LOW during write.
9
CY7C145 CY7C144
Switching Waveforms (continued)
Semaphore Read After Write Timing, Either Side[25]
tAA A0-A 2 VALID ADDRESS tAW SEM tSCE tSD I/O0 tSA R/W tSWRD OE WRITE CYCLE tSOP READ CYCLE
C144-15
tOHA
VALID ADDRESS tACE tSOP
tHA
DATA IN VALID tPWE tHD
DATA OUT VALID
tDOE
Semaphore Contention[26, 27, 28]
A0L-A 2L
MATCH
R/WL SEML tSPS A0R-A 2R MATCH
R/WR SEM R
C144-16
Notes: 25. CE = HIGH for the duration of the above timing (both write and read cycle). 26. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH 27. Semaphores are reset (available to both ports) at cycle start. 28. If tSPS is violated, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore.
10
CY7C145 CY7C144
Switching Waveforms (continued)
Read with BUSY (M/S=HIGH)[20]
tWC ADDRESSR R/WR MATCH tPWE
tSD DATAINR tPS ADDRESSL tBLA BUSYL tDDD DATA OUTL tWDD MATCH VALID
tHD
tBHA tBDD
VALID
C144-17
Write Timing with Busy Input (M/S=LOW)
tPWE
R/W tWB
BUSY
tWH
C144-18
11
CY7C145 CY7C144
Switching Waveforms (continued)
Busy Timing Diagram No. 1 (CE Arbitration)[29] CEL Valid First:
ADDRESS L,R CEL tPS CER tBLC BUSYR
C144-19
ADDRESS MATCH
tBHC
CER Valid First:
ADDRESS L,R CER tPS CEL tBLC BUSYL
C144-20
ADDRESS MATCH
tBHC
Busy Timing Diagram No. 2 (Address Arbitration)[29] Left Address Valid First:
tRC or tWC ADDRESS L ADDRESS MATCH tPS ADDRESS R tBLA BUSY R
C144-21
ADDRESS MISMATCH
tBHA
Right Address Valid First:
tRC or tWC ADDRESS R ADDRESS MATCH tPS ADDRESS L tBLA BUSYL
C144-22
ADDRESS MISMATCH
tBHA
Note: 29. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted
12
CY7C145 CY7C144
Switching Waveforms (continued)
Interrupt Timing Diagrams Left Side Sets INTR:
ADDRESS L CE L R/W L tWC WRITE 1FFF tHA
[30]
INT R tINS [31]
C144-23
Right Side Clears INT R:
ADDRESS R CER tINR [31] R/WR OE R
tRC READ 1FFF
INTR
C144-24
Right Side Sets INT L:
tWC ADDRESS R CE R WRITE 1FFE tHA
[30]
R/W R
INT L tINS [31]
C144-25
Left Side Clears INTL:
ADDRESS R CEL tINR[31] R/WL OEL INTL
tRC READ 1FFE
C144-26
Notes: 30. tHA depends on which enable pin (CEL or R/WL) is deasserted first. 31. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last.
13
CY7C145 CY7C144
Architecture
The CY7C144/5 consists of a an array of 8K words of 8/9 bits each of dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). These control pins permit independent access for reads or writes to any location in memory. To handle simultaneous writes/reads to the same location, a BUSY pin is provided on each port. Two interrupt (INT) pins can be utilized for port-to-port communication. Two semaphore (SEM) control pins are used for allocating shared resources. With the M/S pin, the CY7C144/5 can function as a Master (BUSY pins are outputs) or as a slave (BUSY pins are inputs). The CY7C144/5 has an automatic power-down feature controlled by CE. Each port is provided with its own output enable control (OE), which allows data to be read from the device. in master mode are push-pull outputs and do not require pull-up resistors to operate. Master/Slave An M/S pin is provided in order to expand the word width by configuring the device as either a master or a slave. The BUSY output of the master is connected to the BUSY input of the slave. This will allow the device to interface to a master device with no external components.Writing of slave devices must be delayed until after the BUSY input has settled. Otherwise, the slave chip may begin a write cycle during a contention situation.When presented a HIGH input, the M/S pin allows the device to be used as a master and therefore the BUSY line is an output. BUSY can then be used to send the arbitration outcome to a slave. Semaphore Operation The CY7C144/5 provides eight semaphore latches which are separate from the dual-port memory locations. Semaphores are used to reserve resources that are shared between the two ports.The state of the semaphore indicates that a resource is in use. For example, if the left port wants to request a given resource, it sets a latch by writing a 0 to a semaphore location. The left port then verifies its success in setting the latch by reading it. After writing to the semaphore, SEM or OE must be deasserted for tSOP before attempting to read the semaphore. The semaphore value will be available tSWRD + tDOE after the rising edge of the semaphore write. If the left port was successful (reads a 0), it assumes control over the shared resource, otherwise (reads a 1) it assumes the right port has control and continues to poll the semaphore.When the right side has relinquished control of the semaphore (by writing a 1), the left side will succeed in gaining control of the semaphore. If the left side no longer requires the semaphore, a 1 is written to cancel its request. Semaphores are accessed by asserting SEM LOW. The SEM pin functions as a chip enable for the semaphore latches (CE must remain HIGH during SEM LOW). A0-2 represents the semaphore address. OE and R/W are used in the same manner as a normal memory access.When writing or reading a semaphore, the other address pins have no effect. When writing to the semaphore, only I/O0 is used. If a 0 is written to the left port of an unused semaphore, a 1 will appear at the same semaphore address on the right port. That semaphore can now only be modified by the side showing 0 (the left port in this case). If the left port now relinquishes control by writing a 1 to the semaphore, the semaphore will be set to 1 for both sides. However, if the right port had requested the semaphore (written a 0) while the left port had control, the right port would immediately own the semaphore as soon as the left port released it. Table 3 shows sample semaphore operations. When reading a semaphore, all eight/nine data lines output the semaphore value. The read value is latched in an output register to prevent the semaphore from changing state during a write from the other port. If both ports attempt to access the semaphore within tSPS of each other, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore. Initialization of the semaphore is not automatic and must be reset during initialization program at power-up. All Semaphores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed.
Functional Description
Write Operation Data must be set up for a duration of t SD before the rising edge of R/W in order to guarantee a valid write. A write operation is controlled by either the OE pin (see Write Cycle No.1 waveform) or the R/W pin (see Write Cycle No. 2 waveform). Data can be written to the device t HZOE after the OE is deasserted or tHZWE after the falling edge of R/W. Required inputs for non-contention operations are summarized in Table 1. If a location is being written to by one port and the opposite port attempts to read that location, a port-to-port flowthrough delay must be met before the data is read on the output; otherwise the data read is not deterministic. Data will be valid on the port tDDD after the data is presented on the other port. Read Operation When reading the device, the user must assert both the OE and CE pins. Data will be available tACE after CE or tDOE after OE are asserted. If the user of the CY7C144/5 wishes to access a semaphore flag, then the SEM pin must be asserted instead of the CE pin. Interrupts The interrupt flag (INT) permits communications between ports.When the left port writes to location 1FFF the right port's inter, rupt flag (INTR) is set. This flag is cleared when the right port reads that same location. Setting the left port's interrupt flag (INTL) is accomplished when the right port writes to location 1FFE. This flag is cleared when the left port reads location 1FFE. The message at 1FFF or 1FFE is user-defined. See Table 2 for input requirements for INT. INTR and INTL are push-pull outputs and do not require pull-up resistors to operate. Busy The CY7C144/5 provides on-chip arbitration to alleviate simultaneous memory location access (contention). If both ports' CEs are asserted and an address match occurs within tPS of each other the Busy logic will determine which port has access. If tPS is violated, one port will definitely gain permission to the location, but it is not guaranteed which one. BUSY will be asserted tBLA after an address match or tBLC after CE is taken LOW. BUSYL and BUSYR
14
CY7C145 CY7C144
Table 1. Non-Contending Read/Write Inputs CE H H X H L L L H L X R/W X H X OE X L H X L X X SEM H L X L H H L Outputs I/O0-7/8 High Z Data Out High Z Data In Data Out Data In Operation Power-Down Read Data in Semaphore I/O Lines Disabled Write to Semaphore Read Write Illegal Condition
Table 2. Interrupt Operation Example (assumes BUSYL=BUSYR=HIGH) Left Port Function Set Left INT Reset Left INT Set Right INT Reset Right INT R/W X X L X CE X L L X OE X L X X A0-12 X 1FFE 1FFF X INT L H X X R/W L X X X CE L L X L Right Port OE X L X L A0-12 1FFE X X 1FFF INT X X L H
Table 3. Semaphore Operation Example Function No action Left port writes semaphore Right port writes 0 to semaphore Left port writes 1 to semaphore Left port writes 0 to semaphore Right port writes 1 to semaphore Left port writes 1 to semaphore Right port writes 0 to semaphore Right port writes 1 to semaphore Left port writes 0 to semaphore Left port writes 1 to semaphore I/O0-7/8 Left 1 0 0 1 1 0 1 1 1 0 1 I/O0-7/8 Right 1 1 1 0 0 1 1 0 1 1 1 Semaphore free Left port obtains semaphore Right side is denied access Right port is granted access to semaphore No change. Left port is denied access Left port obtains semaphore No port accessing semaphore address Right port obtains semaphore No port accessing semaphore Left port obtains semaphore No port accessing semaphore Status
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CY7C145 CY7C144
Typical DC and AC Characteristics
OUTPUT SOURCE CURRENT (mA) NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.4 NORMALIZED I CC , I SB NORMALIZED I CC , I 1.2 1.0 0.8 0.6 0.4 0.2 0.0 4.0 4.5 5.0 5.5 6.0
SB
NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE 1.2 ICC 1.0 0.8 0.6 0.4 0.2 0.6 -55 25 125 ISB3 VCC =5.0V VIN =5.0V
OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 200 160 120 80 40 0 0 1.0 2.0 3.0 4.0 5.0 OUTPUT VOLTAGE (V) VCC =5.0V TA =25C
ICC ISB3
SUPPLY VOLTAGE (V)
AMBIENT TEMPERATURE (C)
OUTPUT SINK CURRENT (mA)
NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.4 NORMALIZED t AA NORMALIZED t AA 1.3 1.2 1.1 1.0 0.9 0.8 4.0 4.5 5.0 5.5 6.0 TA =25C 1.6 1.4 1.2 1.0
NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE
OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 140 120 100 80 60 40 20 0 0.0 1.0 2.0 VCC =5.0V TA =25C 3.0 4.0 5.0
VCC =5.0V 0.8 0.6 -55
25
125
SUPPLY VOLTAGE (V)
AMBIENT TEMPERATURE (C)
OUTPUT VOLTAGE (V)
TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE 1.00 NORMALIZED t PC 30.0 25.0 DELTA t AA (ns) 20.0 15.0 10.0 5.0 0.0 0 1.0 2.0 3.0 4.0 5.0 0
TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 1.25 NORMALIZED I CC
NORMALIZED ICC vs. CYCLE TIME VCC =5.0V TA =25C VIN =0.5V 1.0
0.75
0.50
0.75
0.25
VCC =4.5V TA =25C 0 200 400 600 800 1000 0.50 10 28 40 66
SUPPLY VOLTAGE (V)
CAPACITANCE (pF)
CYCLE FREQUENCY (MHz)
16
CY7C145 CY7C144
Ordering Information
8K x8 Dual-Port SRAM Speed (ns) 15 25 Ordering Code CY7C144-15AC CY7C144-15JC CY7C144-25AC CY7C144-25JC CY7C144-25AI CY7C144-25JI 35 CY7C144-35AC CY7C144-35JC CY7C144-35AI CY7C144-35JI 55 CY7C144-55AC CY7C144-55JC CY7C144-55AI CY7C144-55JI 8K x9 Dual-Port SRAM Speed (ns) 15 25 Ordering Code CY7C145-15AC CY7C145-15JC CY7C145-25AC CY7C145-25JC CY7C145-25AI CY7C145-25JI 35 CY7C145-35AC CY7C145-35JC CY7C145-35AI CY7C145-35JI 55 CY7C145-55AC CY7C145-55JC CY7C145-55AI CY7C145-55JI Document #: 38-00163 Package Name A80 J81 A80 J81 A80 J81 A80 J81 A80 J81 A80 J81 A80 J81 Package Type 80-Lead Thin Quad Flat Pack 68-Lead Plastic Leaded Chip Carrier 80-Lead Thin Quad Flat Pack 68-Lead Plastic Leaded Chip Carrier 80-Lead Thin Quad Flat Pack 68-Lead Plastic Leaded Chip Carrier 80-Lead Thin Quad Flat Pack 68-Lead Plastic Leaded Chip Carrier 80-Lead Thin Quad Flat Pack 68-Lead Plastic Leaded Chip Carrier 80-Lead Thin Quad Flat Pack 68-Lead Plastic Leaded Chip Carrier 80-Lead Thin Quad Flat Pack 68-Lead Plastic Leaded Chip Carrier Industrial Commercial Industrial Commercial Industrial Commercial Operating Range Commercial Package Name A65 J81 A65 J81 A65 J81 A65 J81 A65 J81 A65 J81 A65 J81 Package Type 64-Lead Thin Quad Flat Pack 68-Lead Plastic Leaded Chip Carrier 64-Lead Thin Quad Flat Pack 68-Lead Plastic Leaded Chip Carrier 64-Lead Thin Quad Flat Pack 68-Lead Plastic Leaded Chip Carrier 64-Lead Thin Quad Flat Pack 68-Lead Plastic Leaded Chip Carrier 64-Lead Thin Quad Flat Pack 68-Lead Plastic Leaded Chip Carrier 64-Lead Thin Quad Flat Pack 68-Lead Plastic Leaded Chip Carrier 64-Lead Thin Quad Flat Pack 68-Lead Plastic Leaded Chip Carrier Industrial Commercial Industrial Commercial Industrial Commercial Operating Range Commercial
17
CY7C145 CY7C144
Package Diagrams
64-Pin Thin Plastic Quad Flat Pack A65
80-Pin Thin Plastic Quad Flat Pack A80
18
CY7C145 CY7C144
Package Diagrams (continued)
68-Lead Plastic Leaded ChipCarrierJ81
(c) Cypress Semiconductor Corporation, 1996. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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